reform

MNT Reform: Open Source Portable Computer
Log (Feed) | Files | Refs (Tags) | README

reform2-trackball2.kicad_pro (10883B)


      1 {
      2   "board": {
      3     "design_settings": {
      4       "defaults": {
      5         "board_outline_line_width": 0.09999999999999999,
      6         "copper_line_width": 0.19999999999999998,
      7         "copper_text_italic": false,
      8         "copper_text_size_h": 1.5,
      9         "copper_text_size_v": 1.5,
     10         "copper_text_thickness": 0.3,
     11         "copper_text_upright": false,
     12         "courtyard_line_width": 0.049999999999999996,
     13         "dimension_precision": 4,
     14         "dimension_units": 3,
     15         "dimensions": {
     16           "arrow_length": 1270000,
     17           "extension_offset": 500000,
     18           "keep_text_aligned": true,
     19           "suppress_zeroes": false,
     20           "text_position": 0,
     21           "units_format": 1
     22         },
     23         "fab_line_width": 0.09999999999999999,
     24         "fab_text_italic": false,
     25         "fab_text_size_h": 1.0,
     26         "fab_text_size_v": 1.0,
     27         "fab_text_thickness": 0.15,
     28         "fab_text_upright": false,
     29         "other_line_width": 0.09999999999999999,
     30         "other_text_italic": false,
     31         "other_text_size_h": 1.0,
     32         "other_text_size_v": 1.0,
     33         "other_text_thickness": 0.15,
     34         "other_text_upright": false,
     35         "pads": {
     36           "drill": 2.2,
     37           "height": 4.4,
     38           "width": 4.4
     39         },
     40         "silk_line_width": 0.15,
     41         "silk_text_italic": false,
     42         "silk_text_size_h": 1.0,
     43         "silk_text_size_v": 1.0,
     44         "silk_text_thickness": 0.15,
     45         "silk_text_upright": false,
     46         "zones": {
     47           "45_degree_only": false,
     48           "min_clearance": 0.508
     49         }
     50       },
     51       "diff_pair_dimensions": [
     52         {
     53           "gap": 0.0,
     54           "via_gap": 0.0,
     55           "width": 0.0
     56         }
     57       ],
     58       "drc_exclusions": [],
     59       "meta": {
     60         "filename": "board_design_settings.json",
     61         "version": 2
     62       },
     63       "rule_severities": {
     64         "annular_width": "error",
     65         "clearance": "error",
     66         "copper_edge_clearance": "error",
     67         "courtyards_overlap": "error",
     68         "diff_pair_gap_out_of_range": "error",
     69         "diff_pair_uncoupled_length_too_long": "error",
     70         "drill_out_of_range": "error",
     71         "duplicate_footprints": "warning",
     72         "extra_footprint": "warning",
     73         "footprint_type_mismatch": "error",
     74         "hole_clearance": "error",
     75         "hole_near_hole": "error",
     76         "invalid_outline": "error",
     77         "item_on_disabled_layer": "error",
     78         "items_not_allowed": "error",
     79         "length_out_of_range": "error",
     80         "malformed_courtyard": "error",
     81         "microvia_drill_out_of_range": "error",
     82         "missing_courtyard": "ignore",
     83         "missing_footprint": "warning",
     84         "net_conflict": "warning",
     85         "npth_inside_courtyard": "ignore",
     86         "padstack": "error",
     87         "pth_inside_courtyard": "ignore",
     88         "shorting_items": "error",
     89         "silk_over_copper": "warning",
     90         "silk_overlap": "warning",
     91         "skew_out_of_range": "error",
     92         "through_hole_pad_without_hole": "error",
     93         "too_many_vias": "error",
     94         "track_dangling": "warning",
     95         "track_width": "error",
     96         "tracks_crossing": "error",
     97         "unconnected_items": "error",
     98         "unresolved_variable": "error",
     99         "via_dangling": "warning",
    100         "zone_has_empty_net": "error",
    101         "zones_intersect": "error"
    102       },
    103       "rule_severitieslegacy_courtyards_overlap": true,
    104       "rule_severitieslegacy_no_courtyard_defined": false,
    105       "rules": {
    106         "allow_blind_buried_vias": false,
    107         "allow_microvias": false,
    108         "max_error": 0.005,
    109         "min_clearance": 0.0,
    110         "min_copper_edge_clearance": 0.049999999999999996,
    111         "min_hole_clearance": 0.25,
    112         "min_hole_to_hole": 0.25,
    113         "min_microvia_diameter": 0.19999999999999998,
    114         "min_microvia_drill": 0.09999999999999999,
    115         "min_silk_clearance": 0.0,
    116         "min_through_hole_diameter": 0.3,
    117         "min_track_width": 0.19999999999999998,
    118         "min_via_annular_width": 0.049999999999999996,
    119         "min_via_diameter": 0.39999999999999997,
    120         "use_height_for_length_calcs": true
    121       },
    122       "track_widths": [
    123         0.0
    124       ],
    125       "via_dimensions": [
    126         {
    127           "diameter": 0.0,
    128           "drill": 0.0
    129         }
    130       ],
    131       "zones_allow_external_fillets": false,
    132       "zones_use_no_outline": true
    133     },
    134     "layer_presets": []
    135   },
    136   "boards": [],
    137   "cvpcb": {
    138     "equivalence_files": []
    139   },
    140   "erc": {
    141     "erc_exclusions": [],
    142     "meta": {
    143       "version": 0
    144     },
    145     "pin_map": [
    146       [
    147         0,
    148         0,
    149         0,
    150         0,
    151         0,
    152         0,
    153         1,
    154         0,
    155         0,
    156         0,
    157         0,
    158         2
    159       ],
    160       [
    161         0,
    162         2,
    163         0,
    164         1,
    165         0,
    166         0,
    167         1,
    168         0,
    169         2,
    170         2,
    171         2,
    172         2
    173       ],
    174       [
    175         0,
    176         0,
    177         0,
    178         0,
    179         0,
    180         0,
    181         1,
    182         0,
    183         1,
    184         0,
    185         1,
    186         2
    187       ],
    188       [
    189         0,
    190         1,
    191         0,
    192         0,
    193         0,
    194         0,
    195         1,
    196         1,
    197         2,
    198         1,
    199         1,
    200         2
    201       ],
    202       [
    203         0,
    204         0,
    205         0,
    206         0,
    207         0,
    208         0,
    209         1,
    210         0,
    211         0,
    212         0,
    213         0,
    214         2
    215       ],
    216       [
    217         0,
    218         0,
    219         0,
    220         0,
    221         0,
    222         0,
    223         0,
    224         0,
    225         0,
    226         0,
    227         0,
    228         2
    229       ],
    230       [
    231         1,
    232         1,
    233         1,
    234         1,
    235         1,
    236         0,
    237         1,
    238         1,
    239         1,
    240         1,
    241         1,
    242         2
    243       ],
    244       [
    245         0,
    246         0,
    247         0,
    248         1,
    249         0,
    250         0,
    251         1,
    252         0,
    253         0,
    254         0,
    255         0,
    256         2
    257       ],
    258       [
    259         0,
    260         2,
    261         1,
    262         2,
    263         0,
    264         0,
    265         1,
    266         0,
    267         2,
    268         2,
    269         2,
    270         2
    271       ],
    272       [
    273         0,
    274         2,
    275         0,
    276         1,
    277         0,
    278         0,
    279         1,
    280         0,
    281         2,
    282         0,
    283         0,
    284         2
    285       ],
    286       [
    287         0,
    288         2,
    289         1,
    290         1,
    291         0,
    292         0,
    293         1,
    294         0,
    295         2,
    296         0,
    297         0,
    298         2
    299       ],
    300       [
    301         2,
    302         2,
    303         2,
    304         2,
    305         2,
    306         2,
    307         2,
    308         2,
    309         2,
    310         2,
    311         2,
    312         2
    313       ]
    314     ],
    315     "rule_severities": {
    316       "bus_definition_conflict": "error",
    317       "bus_entry_needed": "error",
    318       "bus_label_syntax": "error",
    319       "bus_to_bus_conflict": "error",
    320       "bus_to_net_conflict": "error",
    321       "different_unit_footprint": "error",
    322       "different_unit_net": "error",
    323       "duplicate_reference": "error",
    324       "duplicate_sheet_names": "error",
    325       "extra_units": "error",
    326       "global_label_dangling": "warning",
    327       "hier_label_mismatch": "error",
    328       "label_dangling": "error",
    329       "lib_symbol_issues": "warning",
    330       "multiple_net_names": "warning",
    331       "net_not_bus_member": "warning",
    332       "no_connect_connected": "warning",
    333       "no_connect_dangling": "warning",
    334       "pin_not_connected": "error",
    335       "pin_not_driven": "error",
    336       "pin_to_pin": "warning",
    337       "power_pin_not_driven": "error",
    338       "similar_labels": "warning",
    339       "unannotated": "error",
    340       "unit_value_mismatch": "error",
    341       "unresolved_variable": "error",
    342       "wire_dangling": "error"
    343     }
    344   },
    345   "libraries": {
    346     "pinned_footprint_libs": [],
    347     "pinned_symbol_libs": []
    348   },
    349   "meta": {
    350     "filename": "reform2-trackball2.kicad_pro",
    351     "version": 1
    352   },
    353   "net_settings": {
    354     "classes": [
    355       {
    356         "bus_width": 12.0,
    357         "clearance": 0.2,
    358         "diff_pair_gap": 0.25,
    359         "diff_pair_via_gap": 0.25,
    360         "diff_pair_width": 0.2,
    361         "line_style": 0,
    362         "microvia_diameter": 0.3,
    363         "microvia_drill": 0.1,
    364         "name": "Default",
    365         "pcb_color": "rgba(0, 0, 0, 0.000)",
    366         "schematic_color": "rgba(0, 0, 0, 0.000)",
    367         "track_width": 0.3,
    368         "via_diameter": 0.8,
    369         "via_drill": 0.4,
    370         "wire_width": 6.0
    371       },
    372       {
    373         "bus_width": 12.0,
    374         "clearance": 0.2,
    375         "diff_pair_gap": 0.25,
    376         "diff_pair_via_gap": 0.25,
    377         "diff_pair_width": 0.2,
    378         "line_style": 0,
    379         "microvia_diameter": 0.3,
    380         "microvia_drill": 0.1,
    381         "name": "Fine",
    382         "nets": [
    383           "/D+",
    384           "/D-",
    385           "/PD+",
    386           "/PD-",
    387           "/UD+",
    388           "/UD-",
    389           "MT",
    390           "PROG",
    391           "QSPI_CS",
    392           "QSPI_SCK",
    393           "QSPI_SD0",
    394           "QSPI_SD1",
    395           "QSPI_SD2",
    396           "QSPI_SD3",
    397           "RESET",
    398           "SCL",
    399           "SDA",
    400           "SWC",
    401           "SWD"
    402         ],
    403         "pcb_color": "rgba(0, 0, 0, 0.000)",
    404         "schematic_color": "rgba(0, 0, 0, 0.000)",
    405         "track_width": 0.2,
    406         "via_diameter": 0.6,
    407         "via_drill": 0.3,
    408         "wire_width": 6.0
    409       },
    410       {
    411         "bus_width": 12.0,
    412         "clearance": 0.2,
    413         "diff_pair_gap": 0.25,
    414         "diff_pair_via_gap": 0.25,
    415         "diff_pair_width": 0.2,
    416         "line_style": 0,
    417         "microvia_diameter": 0.3,
    418         "microvia_drill": 0.1,
    419         "name": "PWR",
    420         "nets": [
    421           "+5V",
    422           "GND"
    423         ],
    424         "pcb_color": "rgba(0, 0, 0, 0.000)",
    425         "schematic_color": "rgba(0, 0, 0, 0.000)",
    426         "track_width": 0.4,
    427         "via_diameter": 0.8,
    428         "via_drill": 0.4,
    429         "wire_width": 6.0
    430       }
    431     ],
    432     "meta": {
    433       "version": 2
    434     },
    435     "net_colors": null
    436   },
    437   "pcbnew": {
    438     "last_paths": {
    439       "gencad": "",
    440       "idf": "",
    441       "netlist": "",
    442       "specctra_dsn": "",
    443       "step": "",
    444       "vrml": ""
    445     },
    446     "page_layout_descr_file": ""
    447   },
    448   "schematic": {
    449     "annotate_start_num": 0,
    450     "drawing": {
    451       "default_line_thickness": 6.0,
    452       "default_text_size": 60.0,
    453       "field_names": [],
    454       "intersheets_ref_own_page": false,
    455       "intersheets_ref_prefix": "",
    456       "intersheets_ref_short": false,
    457       "intersheets_ref_show": false,
    458       "intersheets_ref_suffix": "",
    459       "junction_size_choice": 3,
    460       "label_size_ratio": 0.25,
    461       "pin_symbol_size": 0.0,
    462       "text_offset_ratio": 0.08
    463     },
    464     "legacy_lib_dir": "",
    465     "legacy_lib_list": [],
    466     "meta": {
    467       "version": 1
    468     },
    469     "net_format_name": "Pcbnew",
    470     "ngspice": {
    471       "fix_include_paths": true,
    472       "fix_passive_vals": false,
    473       "meta": {
    474         "version": 0
    475       },
    476       "model_mode": 0,
    477       "workbook_filename": ""
    478     },
    479     "page_layout_descr_file": "",
    480     "plot_directory": "../reform2-schematics-pdf/",
    481     "spice_adjust_passive_values": false,
    482     "spice_external_command": "spice \"%I\"",
    483     "subpart_first_id": 65,
    484     "subpart_id_separator": 0
    485   },
    486   "sheets": [
    487     [
    488       "6475547d-3216-45a4-a15c-48314f1dd0f9",
    489       ""
    490     ]
    491   ],
    492   "text_variables": {}
    493 }