reform

commit 11ef25f2ddfb09cc5938463db2951d875801efb2
parent 5f01f4c41bf66004e26a42616a3b4774782bc204
Author: minute <lukas@mntre.com>
Date:   Fri,  7 Oct 2022 13:53:41 +0000

Merge branch 'lpc-fw-spi-fast-clock' into 'master'

LPC fw: spi fast clock

See merge request reform/reform!32
Diffstat:
M
reform2-lpc-fw/src/boards/reform2/board_reform2.c
 | 
15
++++-----------

1 file changed, 4 insertions(+), 11 deletions(-)
diff --git a/reform2-lpc-fw/src/boards/reform2/board_reform2.c b/reform2-lpc-fw/src/boards/reform2/board_reform2.c
@@ -507,7 +507,7 @@ void boardInit(void)
 
   // SPI0 connected to the main SOM (they're controller)
   ssp0Init();
-  ssp0ClockSlow();
+  ssp0ClockFast();
 
   // SPI chip select
   LPC_GPIO->DIR[1] |= (1 << 23);
@@ -962,19 +962,12 @@ void handle_spi_commands() {
 
   // Host must wait while the LPC prepares response buffer
   // If host does not read 8 bytes the previous response buffer will be stuck in here. 
-  uint8_t Dummy = Dummy;
   for (uint8_t i = 0; i < SSP0_FIFOSIZE; i++)
-  {
-    /* Move on only if TX FIFO not full. */
-    // while ((LPC_SSP0->SR & SSP0_SR_TNF_MASK) == SSP0_SR_TNF_FULL);
     LPC_SSP0->DR = spiBuf[i];
 
-    // while ( (LPC_SSP0->SR & SSP0_SR_RNE_MASK) == SSP0_SR_RNE_EMPTY );
-    /* Whenever a byte is written, MISO FIFO counter increments, Clear FIFO
-    on MISO. Otherwise, when sspReceive is called, previous data byte
-    is left in the FIFO. */
-    Dummy = LPC_SSP0->DR;
-  }
+  // Clear RX FIFO
+  for (uint8_t i = 0; i < SSP0_FIFOSIZE; i++)
+    spiBuf[i] = LPC_SSP0->DR;
 
   spi_cmd_state = ST_EXPECT_MAGIC;
   spi_command = 0;