commit b13f9e1e3d28ebe292e740c366e0861e8596e9fd parent a62871719fe3218f8980c4dfa99adf8acbd9e582 Author: mntmn <lukas@mntmn.com> Date: Fri, 14 Jun 2019 22:23:01 +0200 reform2: add schematic pages for display, eth, usb, sd, pcie, hdmi, audio and some chip work Diffstat:
| A | reform2-motherboard/reform2-motherboard/SN65DSI86ZQER/SN65DSI86ZQER.lib | | | 91 | +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
| A | reform2-motherboard/reform2-motherboard/SN65DSI86ZQER/SN65DSI86ZQER.mod | | | 543 | +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
| A | reform2-motherboard/reform2-motherboard/SN65DSI86ZQER/how-to-import.htm | | | 2 | ++ |
| A | reform2-motherboard/reform2-motherboard/reform2-audio.sch | | | 17 | +++++++++++++++++ |
| A | reform2-motherboard/reform2-motherboard/reform2-display.sch | | | 73 | +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
| A | reform2-motherboard/reform2-motherboard/reform2-eth.sch | | | 241 | +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
| A | reform2-motherboard/reform2-motherboard/reform2-hdmi.sch | | | 573 | +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
| M | reform2-motherboard/reform2-motherboard/reform2-motherboard.sch | | | 122 | ++++++++++++++++++++++++++++++++++++++++---------------------------------------- |
| A | reform2-motherboard/reform2-motherboard/reform2-pcie.sch | | | 41 | +++++++++++++++++++++++++++++++++++++++++ |
| M | reform2-motherboard/reform2-motherboard/reform2-power.sch | | | 8 | ++++---- |
| A | reform2-motherboard/reform2-motherboard/reform2-sd.sch | | | 148 | +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
| A | reform2-motherboard/reform2-motherboard/reform2-usb.sch | | | 139 | +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
| M | reform2-motherboard/reform2-motherboard/reform2.lib | | | 532 | +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
13 files changed, 2465 insertions(+), 65 deletions(-)
diff --git a/reform2-motherboard/reform2-motherboard/SN65DSI86ZQER/SN65DSI86ZQER.lib b/reform2-motherboard/reform2-motherboard/SN65DSI86ZQER/SN65DSI86ZQER.lib @@ -0,0 +1,90 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +#(c) SnapEDA 2016 (snapeda.com) +#This work is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License (CC BY-SA) with Design Exception 1.0 +# +# SN65DSI86ZQER +# +DEF SN65DSI86ZQER U 0 40 Y Y 1 L N +F0 "U" -628 1752 50 H V L BNN +F1 "SN65DSI86ZQER" -596 -2192 50 H V L BNN +F2 "BGA64C50P9X9_500X500X100" 0 0 50 H I L BNN +F3 "Texas Instruments" 0 0 50 H I L BNN +F4 "Dual-Channel MIPI® DSI to Embedded DisplayPort™ _eDP _ Bridge 64-BGA MICROSTAR JUNIOR -40 to 85" 0 0 50 H I L BNN +F5 "BGA-64 Texas Instruments" 0 0 50 H I L BNN +F6 "None" 0 0 50 H I L BNN +F7 "SN65DSI86ZQER" 0 0 50 H I L BNN +F8 "Unavailable" 0 0 50 H I L BNN +DRAW +P 2 0 0 10 -600 1700 600 1700 N +P 2 0 0 10 600 1700 600 -2100 N +P 2 0 0 10 600 -2100 -600 -2100 N +P 2 0 0 10 -600 -2100 -600 1700 N +X DA1P H4 -700 1500 100 R 40 40 0 0 I +X VCC D5 700 1400 100 L 40 40 0 0 W +X VCC D6 700 1400 100 L 40 40 0 0 W +X VCC J2 700 1400 100 L 40 40 0 0 W +X VCC J9 700 1400 100 L 40 40 0 0 W +X ML0P F8 700 800 100 L 40 40 0 0 O +X ADDR A1 -700 -1100 100 R 40 40 0 0 B +X GND A8 700 -2000 100 L 40 40 0 0 W +X GND D8 700 -2000 100 L 40 40 0 0 W +X GND E4 700 -2000 100 L 40 40 0 0 W +X GND E5 700 -2000 100 L 40 40 0 0 W +X GND F4 700 -2000 100 L 40 40 0 0 W +X GND F5 700 -2000 100 L 40 40 0 0 W +X GND F6 700 -2000 100 L 40 40 0 0 W +X GND G8 700 -2000 100 L 40 40 0 0 W +X AUXN H9 -700 -1300 100 R 40 40 0 0 B +X DA0N J3 -700 100 100 R 40 40 0 0 B +X DA2P H6 -700 1400 100 R 40 40 0 0 I +X DA3P H7 -700 1300 100 R 40 40 0 0 I +X DACP H5 -700 1200 100 R 40 40 0 0 I +X DB0P C2 -700 1100 100 R 40 40 0 0 I +X DB1P D2 -700 1000 100 R 40 40 0 0 I +X DB2P F2 -700 900 100 R 40 40 0 0 I +X DB3P G2 -700 800 100 R 40 40 0 0 I +X DBCP E2 -700 700 100 R 40 40 0 0 I +X ~EN~ B1 -700 500 100 R 40 40 0 0 I +X GPIO1 A4 700 -300 100 L 40 40 0 0 B +X HPD J8 -700 400 100 R 40 40 0 0 I +X IRQ A3 700 -800 100 L 40 40 0 0 O +X ML1P E8 700 700 100 L 40 40 0 0 O +X ML2P C8 700 600 100 L 40 40 0 0 O +X ML3P B8 700 500 100 L 40 40 0 0 O +X REFCLK A7 -700 300 100 R 40 40 0 0 I C +X SCL H1 -700 -1500 100 R 40 40 0 0 B C +X SDA J1 -700 -1600 100 R 40 40 0 0 B +X TEST1 B3 -700 -1800 100 R 40 40 0 0 I +X TEST2 B5 -700 -1900 100 R 40 40 0 0 B +X TEST3 B7 -700 -2000 100 R 40 40 0 0 B +X VCCA A9 700 1300 100 L 40 40 0 0 W +X VCCA B2 700 1300 100 L 40 40 0 0 W +X VCCA E6 700 1300 100 L 40 40 0 0 W +X VCCA G9 700 1300 100 L 40 40 0 0 W +X VCCA H2 700 1300 100 L 40 40 0 0 W +X VCCIO A2 700 1200 100 L 40 40 0 0 W +X VCCIO B6 700 1200 100 L 40 40 0 0 W +X VPLL D9 700 1100 100 L 40 40 0 0 W +X ML0N F9 700 400 100 L 40 40 0 0 O +X ML1N E9 700 300 100 L 40 40 0 0 O +X ML2N C9 700 200 100 L 40 40 0 0 O +X ML3N B9 700 100 100 L 40 40 0 0 O +X GPIO2 A5 700 -400 100 L 40 40 0 0 B +X GPIO3 A6 700 -500 100 L 40 40 0 0 B +X GPIO4 B4 700 -600 100 L 40 40 0 0 B +X AUXP H8 -700 -1200 100 R 40 40 0 0 B +X DA1N J4 -700 0 100 R 40 40 0 0 I +X DA2N J6 -700 -100 100 R 40 40 0 0 I +X DA3N J7 -700 -200 100 R 40 40 0 0 I +X DACN J5 -700 -300 100 R 40 40 0 0 I +X DB0N C1 -700 -400 100 R 40 40 0 0 I +X DB1N D1 -700 -500 100 R 40 40 0 0 I +X DB2N F1 -700 -600 100 R 40 40 0 0 I +X DB3N G1 -700 -700 100 R 40 40 0 0 I +X DBCN E1 -700 -800 100 R 40 40 0 0 I +X DA0P H3 -700 1600 100 R 40 40 0 0 I +ENDDRAW +ENDDEF +# +# End Library +\ No newline at end of file diff --git a/reform2-motherboard/reform2-motherboard/SN65DSI86ZQER/SN65DSI86ZQER.mod b/reform2-motherboard/reform2-motherboard/SN65DSI86ZQER/SN65DSI86ZQER.mod @@ -0,0 +1,543 @@ +PCBNEW-LibModule-V1 +# encoding utf-8 +Units mm +$INDEX +BGA64C50P9X9_500X500X100 +$EndINDEX +$MODULE BGA64C50P9X9_500X500X100 +Po 0 0 0 15 00000000 00000000 ~~ +Li BGA64C50P9X9_500X500X100 +Cd +Sc 00000000 +At SMD +Op 0 0 0 +.SolderMask 0 +.SolderPaste 0 +T0 -1.78455 -3.06123 0.481011 0.481011 0 0.05 N V 21 "BGA64C50P9X9_500X500X100" +T1 -1.22988 3.20529 0.481516 0.481516 0 0.05 N V 21 "VAL**" +DS -2.5 -2.5 2.5 -2.5 0.127 27 +DS -2.5 -2.5 -2.5 2.5 0.127 27 +DS 2.5 2.5 -2.5 2.5 0.127 27 +DS 2.5 2.5 2.5 -2.5 0.127 27 +DC -2.8 -2 -2.65 -2 0 21 +DS -2.75 -2.75 2.75 -2.75 0.05 26 +DS 2.75 -2.75 2.75 2.75 0.05 26 +DS 2.75 2.75 -2.75 2.75 0.05 26 +DS -2.75 2.75 -2.75 -2.75 0.05 26 +DS -2.5 -2.5 2.5 -2.5 0.127 21 +DS 2.5 -2.5 2.5 2.5 0.127 21 +DS 2.5 2.5 -2.5 2.5 0.127 21 +DS -2.5 2.5 -2.5 -2.5 0.127 21 +$PAD +Sh "A1" C 0.24 0.24 0 0 0 +At SMD N 00888000 +.SolderMask 0 +.SolderPaste 0 +Ne 0 "" +Po -2 -2 +$EndPAD +$PAD +Sh "A2" C 0.24 0.24 0 0 0 +At SMD N 00888000 +.SolderMask 0 +.SolderPaste 0 +Ne 0 "" +Po -1.5 -2 +$EndPAD +$PAD +Sh "A3" C 0.24 0.24 0 0 0 +At SMD N 00888000 +.SolderMask 0 +.SolderPaste 0 +Ne 0 "" +Po -1 -2 +$EndPAD +$PAD +Sh "A4" C 0.24 0.24 0 0 0 +At SMD N 00888000 +.SolderMask 0 +.SolderPaste 0 +Ne 0 "" +Po -0.5 -2 +$EndPAD +$PAD +Sh "A5" C 0.24 0.24 0 0 0 +At SMD N 00888000 +.SolderMask 0 +.SolderPaste 0 +Ne 0 "" +Po 0 -2 +$EndPAD +$PAD +Sh "A6" C 0.24 0.24 0 0 0 +At SMD N 00888000 +.SolderMask 0 +.SolderPaste 0 +Ne 0 "" +Po 0.5 -2 +$EndPAD +$PAD +Sh "A7" C 0.24 0.24 0 0 0 +At SMD N 00888000 +.SolderMask 0 +.SolderPaste 0 +Ne 0 "" +Po 1 -2 +$EndPAD +$PAD +Sh "A8" C 0.24 0.24 0 0 0 +At SMD N 00888000 +.SolderMask 0 +.SolderPaste 0 +Ne 0 "" +Po 1.5 -2 +$EndPAD +$PAD +Sh "A9" C 0.24 0.24 0 0 0 +At SMD N 00888000 +.SolderMask 0 +.SolderPaste 0 +Ne 0 "" +Po 2 -2 +$EndPAD +$PAD +Sh "B1" C 0.24 0.24 0 0 0 +At SMD N 00888000 +.SolderMask 0 +.SolderPaste 0 +Ne 0 "" +Po -2 -1.5 +$EndPAD +$PAD +Sh "B2" C 0.24 0.24 0 0 0 +At SMD N 00888000 +.SolderMask 0 +.SolderPaste 0 +Ne 0 "" +Po -1.5 -1.5 +$EndPAD +$PAD +Sh "B3" C 0.24 0.24 0 0 0 +At SMD N 00888000 +.SolderMask 0 +.SolderPaste 0 +Ne 0 "" +Po -1 -1.5 +$EndPAD +$PAD +Sh "B4" C 0.24 0.24 0 0 0 +At SMD N 00888000 +.SolderMask 0 +.SolderPaste 0 +Ne 0 "" +Po -0.5 -1.5 +$EndPAD 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"" +Po -1 1.5 +$EndPAD +$PAD +Sh "E4" C 0.24 0.24 0 0 0 +At SMD N 00888000 +.SolderMask 0 +.SolderPaste 0 +Ne 0 "" +Po -0.5 0 +$EndPAD +$PAD +Sh "F4" C 0.24 0.24 0 0 0 +At SMD N 00888000 +.SolderMask 0 +.SolderPaste 0 +Ne 0 "" +Po -0.5 0.5 +$EndPAD +$PAD +Sh "H4" C 0.24 0.24 0 0 0 +At SMD N 00888000 +.SolderMask 0 +.SolderPaste 0 +Ne 0 "" +Po -0.5 1.5 +$EndPAD +$PAD +Sh "D5" C 0.24 0.24 0 0 0 +At SMD N 00888000 +.SolderMask 0 +.SolderPaste 0 +Ne 0 "" +Po 0 -0.5 +$EndPAD +$PAD +Sh "E5" C 0.24 0.24 0 0 0 +At SMD N 00888000 +.SolderMask 0 +.SolderPaste 0 +Ne 0 "" +Po 0 0 +$EndPAD +$PAD +Sh "F5" C 0.24 0.24 0 0 0 +At SMD N 00888000 +.SolderMask 0 +.SolderPaste 0 +Ne 0 "" +Po 0 0.5 +$EndPAD +$PAD +Sh "H5" C 0.24 0.24 0 0 0 +At SMD N 00888000 +.SolderMask 0 +.SolderPaste 0 +Ne 0 "" +Po 0 1.5 +$EndPAD +$PAD +Sh "D6" C 0.24 0.24 0 0 0 +At SMD N 00888000 +.SolderMask 0 +.SolderPaste 0 +Ne 0 "" +Po 0.5 -0.5 +$EndPAD +$PAD +Sh "E6" C 0.24 0.24 0 0 0 +At SMD N 00888000 +.SolderMask 0 +.SolderPaste 0 +Ne 0 "" +Po 0.5 0 +$EndPAD +$PAD +Sh "F6" C 0.24 0.24 0 0 0 +At SMD N 00888000 +.SolderMask 0 +.SolderPaste 0 +Ne 0 "" +Po 0.5 0.5 +$EndPAD +$PAD +Sh "H6" C 0.24 0.24 0 0 0 +At SMD N 00888000 +.SolderMask 0 +.SolderPaste 0 +Ne 0 "" +Po 0.5 1.5 +$EndPAD +$PAD +Sh "H7" C 0.24 0.24 0 0 0 +At SMD N 00888000 +.SolderMask 0 +.SolderPaste 0 +Ne 0 "" +Po 1 1.5 +$EndPAD +$PAD +Sh "C8" C 0.24 0.24 0 0 0 +At SMD N 00888000 +.SolderMask 0 +.SolderPaste 0 +Ne 0 "" +Po 1.5 -1 +$EndPAD +$PAD +Sh "D8" C 0.24 0.24 0 0 0 +At SMD N 00888000 +.SolderMask 0 +.SolderPaste 0 +Ne 0 "" +Po 1.5 -0.5 +$EndPAD +$PAD +Sh "E8" C 0.24 0.24 0 0 0 +At SMD N 00888000 +.SolderMask 0 +.SolderPaste 0 +Ne 0 "" +Po 1.5 0 +$EndPAD +$PAD +Sh "F8" C 0.24 0.24 0 0 0 +At SMD N 00888000 +.SolderMask 0 +.SolderPaste 0 +Ne 0 "" +Po 1.5 0.5 +$EndPAD +$PAD +Sh "G8" C 0.24 0.24 0 0 0 +At SMD N 00888000 +.SolderMask 0 +.SolderPaste 0 +Ne 0 "" +Po 1.5 1 +$EndPAD +$PAD +Sh "H8" C 0.24 0.24 0 0 0 +At SMD N 00888000 +.SolderMask 0 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http-equiv="refresh" content="0; url=https://www.snapeda.com/about/import/"> <script type="text/javascript">window.location.href="https://www.snapeda.com/about/import/" </script> <title>Page Redirection</title> </head> <body> If you are not redirected automatically, follow this <a href="https://www.snapeda.com/about/import/">link to the import guide</a>. </body></html> +\ No newline at end of file diff --git a/reform2-motherboard/reform2-motherboard/reform2-audio.sch b/reform2-motherboard/reform2-motherboard/reform2-audio.sch @@ -0,0 +1,17 @@ +EESchema Schematic File Version 4 +LIBS:reform2-motherboard-cache +EELAYER 29 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 9 9 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$EndSCHEMATC diff --git a/reform2-motherboard/reform2-motherboard/reform2-display.sch b/reform2-motherboard/reform2-motherboard/reform2-display.sch @@ -0,0 +1,73 @@ +EESchema Schematic File Version 4 +LIBS:reform2-motherboard-cache +EELAYER 29 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 5 9 +Title "MNT Reform 2 Internal Display" +Date "2019-06-14" +Rev "0.1" +Comp "MNT Research GmbH" +Comment1 "https://mntre.com" +Comment2 "Engineer: Lukas F. Hartmann" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L reform2:SN65DSI86ZQER U? +U 1 1 5D1D2542 +P 4950 3450 +F 0 "U?" H 4400 5250 50 0000 C CNN +F 1 "SN65DSI86ZQER" H 4650 1250 50 0000 C CNN +F 2 "BGA64C50P9X9_500X500X100" H 4400 800 50 0001 L BNN +F 3 "" H 4950 3450 50 0001 L BNN +F 4 "Dual-Channel MIPI® DSI to Embedded DisplayPort™ _eDP _ Bridge 64-BGA MICROSTAR JUNIOR -40 to 85" H 2850 950 50 0001 L BNN "Field4" + 1 4950 3450 + 1 0 0 -1 +$EndComp +$Comp +L power:GND #PWR? +U 1 1 5D1D45E5 +P 5300 5800 +F 0 "#PWR?" H 5300 5550 50 0001 C CNN +F 1 "GND" H 5305 5627 50 0000 C CNN +F 2 "" H 5300 5800 50 0001 C CNN +F 3 "" H 5300 5800 50 0001 C CNN + 1 5300 5800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5100 5650 5100 5700 +Wire Wire Line + 5100 5700 5200 5700 +Wire Wire Line + 5500 5700 5500 5650 +Wire Wire Line + 5400 5650 5400 5700 +Connection ~ 5400 5700 +Wire Wire Line + 5400 5700 5500 5700 +Wire Wire Line + 5300 5650 5300 5700 +Connection ~ 5300 5700 +Wire Wire Line + 5300 5700 5400 5700 +Wire Wire Line + 5200 5650 5200 5700 +Connection ~ 5200 5700 +Wire Wire Line + 5200 5700 5300 5700 +Wire Wire Line + 5300 5700 5300 5800 +NoConn ~ 4250 2950 +NoConn ~ 4250 3050 +NoConn ~ 4250 3150 +NoConn ~ 4250 3250 +NoConn ~ 4250 3350 +NoConn ~ 4250 3450 +NoConn ~ 4250 3550 +NoConn ~ 4250 3650 +NoConn ~ 4250 3750 +NoConn ~ 4250 3850 +$EndSCHEMATC diff --git a/reform2-motherboard/reform2-motherboard/reform2-eth.sch b/reform2-motherboard/reform2-motherboard/reform2-eth.sch @@ -0,0 +1,241 @@ +EESchema Schematic File Version 4 +LIBS:reform2-motherboard-cache +EELAYER 29 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 4 9 +Title "MNT Reform 2 Ethernet" +Date "2019-06-14" +Rev "0.1" +Comp "MNT Research GmbH" +Comment1 "https://mntre.com" +Comment2 "Engineer: Lukas F. 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H 6750 4600 50 0001 C CNN +F 1 "+3V3" H 6750 4890 50 0000 C CNN +F 2 "" H 6750 4750 50 0001 C CNN +F 3 "" H 6750 4750 50 0001 C CNN + 1 6750 4750 + 1 0 0 -1 +$EndComp +$Comp +L reform-motherboard-rescue:C_Small C? +U 1 1 5A04FD85 +P 6500 5000 +F 0 "C?" H 6510 5070 50 0000 L CNN +F 1 "0.1uF" H 6510 4920 50 0000 L CNN +F 2 "Capacitors_SMD:C_0603_HandSoldering" H 6500 5000 50 0001 C CNN +F 3 "" H 6500 5000 50 0001 C CNN + 1 6500 5000 + 1 0 0 -1 +$EndComp +$Comp +L reform-motherboard-rescue:GND #PWR? +U 1 1 5A04FDB4 +P 6500 5100 +F 0 "#PWR?" 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H 3450 1861 50 0000 C CNN +F 1 "KSZ9031RNXCA" H 3450 1770 50 0000 C CNN +F 2 "Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm" H 3900 2000 50 0001 L CNN +F 3 "http://ww1.microchip.com/downloads/en/DeviceDoc/00002117C.pdf" H 3450 1900 50 0001 C CNN + 1 3450 3550 + 1 0 0 -1 +$EndComp +Text GLabel 4750 4350 2 60 BiDi ~ 0 +TRD0_N +Text GLabel 4750 4250 2 60 BiDi ~ 0 +TRD0_P +Text GLabel 4750 3950 2 60 BiDi ~ 0 +TRD1_N +Text GLabel 4750 4050 2 60 BiDi ~ 0 +TRD1_P +Text GLabel 4750 3650 2 60 BiDi ~ 0 +TRD2_N +Text GLabel 4750 3750 2 60 BiDi ~ 0 +TRD2_P +Text GLabel 4750 3350 2 60 BiDi ~ 0 +TRD3_N +Text GLabel 4750 3450 2 60 BiDi ~ 0 +TRD3_P +Text GLabel 2150 4350 0 60 Input ~ 0 +ENET_LED_LINK +Text GLabel 2150 4250 0 60 Input ~ 0 +ENET_LED_RX +$EndSCHEMATC diff --git a/reform2-motherboard/reform2-motherboard/reform2-hdmi.sch b/reform2-motherboard/reform2-motherboard/reform2-hdmi.sch @@ -0,0 +1,573 @@ +EESchema Schematic File Version 4 +LIBS:reform2-motherboard-cache +EELAYER 29 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 8 9 +Title "MNT Reform 2 External Display" +Date "2019-06-14" +Rev "0.1" +Comp "MNT Research GmbH" +Comment1 "https://mntre.com" +Comment2 "Engineer: Lukas F. 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H 8750 5550 50 0001 C CNN +F 1 "+3V3" H 8765 5873 50 0000 C CNN +F 2 "" H 8750 5700 50 0001 C CNN +F 3 "" H 8750 5700 50 0001 C CNN + 1 8750 5700 + 1 0 0 -1 +$EndComp +$Comp +L Device:R_Small R? +U 1 1 5D185434 +P 9000 5750 +F 0 "R?" V 8804 5750 50 0000 C CNN +F 1 "47k" V 8895 5750 50 0000 C CNN +F 2 "" H 9000 5750 50 0001 C CNN +F 3 "~" H 9000 5750 50 0001 C CNN + 1 9000 5750 + 0 1 1 0 +$EndComp +Wire Wire Line + 9100 5750 9150 5750 +Wire Wire Line + 8900 5750 8750 5750 +Wire Wire Line + 8750 5750 8750 5700 +NoConn ~ 7650 3200 +Wire Wire Line + 5900 5700 7450 5700 +Wire Wire Line + 7450 5700 7450 2700 +Wire Wire Line + 7450 2700 7650 2700 +Text GLabel 5900 5600 2 50 BiDi ~ 0 +HDMI_CEC +$EndSCHEMATC diff --git a/reform2-motherboard/reform2-motherboard/reform2-motherboard.sch b/reform2-motherboard/reform2-motherboard/reform2-motherboard.sch @@ -4,13 +4,13 @@ EELAYER 29 0 EELAYER END $Descr A2 23386 16535 encoding utf-8 -Sheet 1 2 -Title "REFORM 2" -Date "2019-04-25" -Rev "" +Sheet 1 9 +Title "MNT Reform 2" +Date "2019-06-14" +Rev "0.1" Comp "MNT Research GmbH" -Comment1 "" -Comment2 "" +Comment1 "https://mntre.com" +Comment2 "Engineer: Lukas F. Hartmann" Comment3 "" Comment4 "" $EndDescr @@ -58,28 +58,6 @@ NoConn ~ 10500 14100 NoConn ~ 2500 9500 NoConn ~ 2500 9600 NoConn ~ 2500 9700 -$Comp -L Connector:HDMI_A J13 -U 1 1 5CCAF72C -P 20650 4750 -F 0 "J13" H 21080 4796 50 0000 L CNN -F 1 "HDMI_A" H 21080 4705 50 0000 L CNN -F 2 "" H 20675 4750 50 0001 C CNN -F 3 "https://en.wikipedia.org/wiki/HDMI" H 20675 4750 50 0001 C CNN - 1 20650 4750 - 1 0 0 -1 -$EndComp -$Comp -L Connector:SD_Card J14 -U 1 1 5CCB07EE -P 20300 7550 -F 0 "J14" H 20300 8215 50 0000 C CNN -F 1 "SD_Card" H 20300 8124 50 0000 C CNN -F 2 "" H 20300 7550 50 0001 C CNN -F 3 "http://portal.fciconnect.com/Comergent//fci/drawing/10067847.pdf" H 20300 7550 50 0001 C CNN - 1 20300 7550 - 1 0 0 -1 -$EndComp Text GLabel 2500 10900 0 50 Input ~ 0 HDMI_D0+ Text GLabel 2500 11000 0 50 Input ~ 0 @@ -96,18 +74,6 @@ Text GLabel 2500 10700 0 50 Input ~ 0 HDMI_D1+ Text GLabel 2500 10800 0 50 Input ~ 0 HDMI_D1- -Text GLabel 19000 4050 0 50 Input ~ 0 -HDMI_D2- -Text GLabel 19000 3950 0 50 Input ~ 0 -HDMI_D2+ -Text GLabel 19000 4250 0 50 Input ~ 0 -HDMI_D1- -Text GLabel 19000 4150 0 50 Input ~ 0 -HDMI_D1+ -Text GLabel 19000 4650 0 50 Input ~ 0 -HDMI_D3- -Text GLabel 19000 4550 0 50 Input ~ 0 -HDMI_D3+ Connection ~ 12500 14600 Wire Wire Line 12500 14750 12500 14600 @@ -513,10 +479,6 @@ Wire Wire Line 4500 8200 4500 8300 Wire Wire Line 4500 8100 4500 8200 -Text GLabel 19000 4450 0 50 Input ~ 0 -HDMI_D0- -Text GLabel 19000 4350 0 50 Input ~ 0 -HDMI_D0+ $Comp L reform2:phycore-imx8m-alpha U1 U 1 1 5CC23859 @@ -544,26 +506,64 @@ Text GLabel 2500 13400 0 50 Input ~ 0 SD2_WP Text GLabel 2500 13300 0 50 Input ~ 0 SD2_CD -Text GLabel 18550 7850 0 50 Input ~ 0 -SD2_DATA0 -Text GLabel 18550 7950 0 50 Input ~ 0 -SD2_DATA1 -Text GLabel 18550 7150 0 50 Input ~ 0 -SD2_DATA2 -Text GLabel 18550 7250 0 50 Input ~ 0 -SD2_DATA3 -Text GLabel 18550 7350 0 50 Input ~ 0 -SD2_CMD -Text GLabel 18550 7650 0 50 Input ~ 0 -SD2_CLK -Text GLabel 18550 8100 0 50 Input ~ 0 -SD2_WP -Text GLabel 18550 8200 0 50 Input ~ 0 -SD2_CD $Sheet -S 20850 12750 500 150 +S 18750 11100 500 150 U 5CC81028 F0 "Reform 2 Power" 50 F1 "reform2-power.sch" 50 $EndSheet +$Sheet +S 18750 11500 500 150 +U 5D06A2FD +F0 "Reform 2 USB" 50 +F1 "reform2-usb.sch" 50 +$EndSheet +$Sheet +S 18750 11900 500 150 +U 5D06A32E +F0 "Reform 2 Ethernet" 50 +F1 "reform2-eth.sch" 50 +$EndSheet +$Sheet +S 18750 12300 500 150 +U 5D06A7B6 +F0 "Reform 2 Display" 50 +F1 "reform2-display.sch" 50 +$EndSheet +$Sheet +S 18750 12700 500 150 +U 5D06AC46 +F0 "Reform 2 PCIe" 50 +F1 "reform2-pcie.sch" 50 +$EndSheet +$Sheet +S 18750 13100 500 150 +U 5D0CA3EB +F0 "Reform 2 SD Card" 50 +F1 "reform2-sd.sch" 50 +$EndSheet +$Sheet +S 18750 13500 500 150 +U 5D0D8363 +F0 "Reform 2 HDMI" 50 +F1 "reform2-hdmi.sch" 50 +$EndSheet +Text GLabel 2500 12300 0 50 Output ~ 0 +USB1_TX_N +Text GLabel 2500 12400 0 50 Output ~ 0 +USB1_TX_P +Text GLabel 2500 12500 0 50 Output ~ 0 +USB1_DN +Text GLabel 2500 12600 0 50 Output ~ 0 +USB1_DP +Text GLabel 2500 12100 0 50 Input ~ 0 +USB1_RX_N +Text GLabel 2500 12200 0 50 Input ~ 0 +USB1_RX_P +$Sheet +S 18750 13900 500 150 +U 5D1F6C04 +F0 "Reform 2 Audio" 50 +F1 "reform2-audio.sch" 50 +$EndSheet $EndSCHEMATC diff --git a/reform2-motherboard/reform2-motherboard/reform2-pcie.sch b/reform2-motherboard/reform2-motherboard/reform2-pcie.sch @@ -0,0 +1,41 @@ +EESchema Schematic File Version 4 +LIBS:reform2-motherboard-cache +EELAYER 29 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 6 9 +Title "MNT Reform 2 PCIe" +Date "2019-06-14" +Rev "0.1" +Comp "MNT Research GmbH" +Comment1 "https://mntre.com" +Comment2 "Engineer: Lukas F. Hartmann" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L reform-motherboard-rescue:MPCIE-Socket U? +U 1 1 5D1F1F73 +P 4100 3550 +F 0 "U?" H 4100 4987 60 0000 C CNN +F 1 "MPCIE-Socket" H 4100 4881 60 0000 C CNN +F 2 "" H 4200 2550 60 0000 C CNN +F 3 "" H 4200 2550 60 0000 C CNN + 1 4100 3550 + 1 0 0 -1 +$EndComp +$Comp +L reform-motherboard-rescue:MPCIE-Socket U? +U 1 1 5D1F2FE0 +P 7350 3550 +F 0 "U?" H 7350 4987 60 0000 C CNN +F 1 "MPCIE-Socket" H 7350 4881 60 0000 C CNN +F 2 "" H 7450 2550 60 0000 C CNN +F 3 "" H 7450 2550 60 0000 C CNN + 1 7350 3550 + 1 0 0 -1 +$EndComp +Text Notes 6650 1850 0 50 ~ 0 +TODO: mSATA controller or M.2 SSD? +$EndSCHEMATC diff --git a/reform2-motherboard/reform2-motherboard/reform2-power.sch b/reform2-motherboard/reform2-motherboard/reform2-power.sch @@ -4,13 +4,13 @@ EELAYER 29 0 EELAYER END $Descr A3 16535 11693 encoding utf-8 -Sheet 2 2 -Title "MNT Reform V2 Power System" -Date "2019-06-12" +Sheet 2 9 +Title "MNT Reform 2 Power System" +Date "2019-06-14" Rev "0.1" Comp "MNT Research GmbH" Comment1 "https://mntre.com" -Comment2 "" +Comment2 "Engineer: Lukas F. Hartmann" Comment3 "" Comment4 "" $EndDescr diff --git a/reform2-motherboard/reform2-motherboard/reform2-sd.sch b/reform2-motherboard/reform2-motherboard/reform2-sd.sch @@ -0,0 +1,148 @@ +EESchema Schematic File Version 4 +LIBS:reform2-motherboard-cache +EELAYER 29 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 7 9 +Title "MNT Reform 2 SD Card" +Date "2019-06-14" +Rev "0.1" +Comp "MNT Research GmbH" +Comment1 "https://mntre.com" +Comment2 "Engineer: Lukas F. Hartmann" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L Connector:SD_Card J? +U 1 1 5D0E6993 +P 6200 3450 +F 0 "J?" H 6200 4115 50 0000 C CNN +F 1 "SD_Card" H 6200 4024 50 0000 C CNN +F 2 "" H 6200 3450 50 0001 C CNN +F 3 "http://portal.fciconnect.com/Comergent//fci/drawing/10067847.pdf" H 6200 3450 50 0001 C CNN + 1 6200 3450 + 1 0 0 -1 +$EndComp +Text GLabel 4450 3750 0 50 Input ~ 0 +SD2_DATA0 +Text GLabel 4450 3850 0 50 Input ~ 0 +SD2_DATA1 +Text GLabel 4450 3050 0 50 Input ~ 0 +SD2_DATA2 +Text GLabel 4450 3150 0 50 Input ~ 0 +SD2_DATA3 +Text GLabel 4450 3250 0 50 Input ~ 0 +SD2_CMD +Text GLabel 4450 3550 0 50 Input ~ 0 +SD2_CLK +Text GLabel 7550 3350 2 50 Input ~ 0 +SD2_WP +Text GLabel 7550 3250 2 50 Input ~ 0 +SD2_CD +Wire Wire Line + 4450 3050 5300 3050 +Wire Wire Line + 5300 3150 4450 3150 +Wire Wire Line + 4450 3750 5300 3750 +Wire Wire Line + 5300 3850 4450 3850 +Wire Wire Line + 7550 3250 7350 3250 +Wire Wire Line + 7100 3350 7550 3350 +$Comp +L Device:R_Small R? +U 1 1 5D1CB92A +P 7350 2850 +F 0 "R?" H 7409 2896 50 0000 L CNN +F 1 "R_Small" H 7409 2805 50 0000 L CNN +F 2 "" H 7350 2850 50 0001 C CNN +F 3 "~" H 7350 2850 50 0001 C CNN + 1 7350 2850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7350 3250 7350 2950 +Connection ~ 7350 3250 +Wire Wire Line + 7350 3250 7100 3250 +$Comp +L power:+3V3 #PWR? +U 1 1 5D1CBCC0 +P 7350 2700 +F 0 "#PWR?" H 7350 2550 50 0001 C CNN +F 1 "+3V3" H 7365 2873 50 0000 C CNN +F 2 "" H 7350 2700 50 0001 C CNN +F 3 "" H 7350 2700 50 0001 C CNN + 1 7350 2700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7350 2700 7350 2750 +$Comp +L power:+3V3 #PWR? +U 1 1 5D1CC1EA +P 4850 2750 +F 0 "#PWR?" H 4850 2600 50 0001 C CNN +F 1 "+3V3" H 4865 2923 50 0000 C CNN +F 2 "" H 4850 2750 50 0001 C CNN +F 3 "" H 4850 2750 50 0001 C CNN + 1 4850 2750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4850 2750 4850 3450 +Wire Wire Line + 4850 3450 5300 3450 +$Comp +L power:GND #PWR? +U 1 1 5D1CD57E +P 5300 3350 +F 0 "#PWR?" H 5300 3100 50 0001 C CNN +F 1 "GND" V 5305 3222 50 0000 R CNN +F 2 "" H 5300 3350 50 0001 C CNN +F 3 "" H 5300 3350 50 0001 C CNN + 1 5300 3350 + 0 1 -1 0 +$EndComp +Wire Wire Line + 5300 3250 4450 3250 +Wire Wire Line + 5300 3550 4450 3550 +$Comp +L power:GND #PWR? +U 1 1 5D1CDDEB +P 5300 3650 +F 0 "#PWR?" H 5300 3400 50 0001 C CNN +F 1 "GND" V 5305 3522 50 0000 R CNN +F 2 "" H 5300 3650 50 0001 C CNN +F 3 "" H 5300 3650 50 0001 C CNN + 1 5300 3650 + 0 1 -1 0 +$EndComp +$Comp +L power:GND #PWR? +U 1 1 5D1CE3E8 +P 7200 3750 +F 0 "#PWR?" H 7200 3500 50 0001 C CNN +F 1 "GND" H 7205 3577 50 0000 C CNN +F 2 "" H 7200 3750 50 0001 C CNN +F 3 "" H 7200 3750 50 0001 C CNN + 1 7200 3750 + -1 0 0 -1 +$EndComp +Wire Wire Line + 7200 3750 7200 3650 +Wire Wire Line + 7200 3650 7100 3650 +Wire Wire Line + 7100 3550 7200 3550 +Wire Wire Line + 7200 3550 7200 3650 +Connection ~ 7200 3650 +Text Notes 5450 2400 0 50 ~ 0 +TODO: isolation / level shift? +$EndSCHEMATC diff --git a/reform2-motherboard/reform2-motherboard/reform2-usb.sch b/reform2-motherboard/reform2-motherboard/reform2-usb.sch @@ -0,0 +1,139 @@ +EESchema Schematic File Version 4 +LIBS:reform2-motherboard-cache +EELAYER 29 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 3 9 +Title "MNT Reform 2 USB" +Date "2019-06-14" +Rev "0.1" +Comp "MNT Research GmbH" +Comment1 "https://mntre.com" +Comment2 "Engineer: Lukas F. Hartmann" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L Interface_USB:TUSB8041 U? +U 1 1 5D114731 +P 8350 3250 +AR Path="/5D114731" Ref="U?" Part="1" +AR Path="/5D06A2FD/5D114731" Ref="U?" Part="1" +F 0 "U?" H 7450 1250 50 0000 C CNN +F 1 "TUSB8041" H 7450 1150 50 0000 C CNN +F 2 "Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm_ThermalVias" H 9550 5250 50 0001 L CNN +F 3 "http://www.ti.com/lit/ds/symlink/tusb8041.pdf" H 8050 3450 50 0001 C CNN + 1 8350 3250 + 1 0 0 -1 +$EndComp +$Comp +L reform-motherboard-rescue:Crystal_Small Y? +U 1 1 5D1A9B07 +P 3550 2200 +F 0 "Y?" H 3550 2300 50 0000 C CNN +F 1 "24MHz" H 3550 2100 50 0000 C CNN +F 2 "Crystals:Crystal_SMD_5032-2pin_5.0x3.2mm_HandSoldering" H 3550 2200 50 0001 C CNN +F 3 "" H 3550 2200 50 0001 C CNN + 1 3550 2200 + 1 0 0 -1 +$EndComp +$Comp +L reform-motherboard-rescue:R_Small R? +U 1 1 5D1A9B0D +P 3550 1950 +F 0 "R?" H 3580 1970 50 0000 L CNN +F 1 "1M" H 3580 1910 50 0000 L CNN +F 2 "Resistors_SMD:R_0603_HandSoldering" H 3550 1950 50 0001 C CNN +F 3 "" H 3550 1950 50 0001 C CNN + 1 3550 1950 + 0 -1 -1 0 +$EndComp +$Comp +L reform-motherboard-rescue:C_Small C? +U 1 1 5D1A9B13 +P 3850 2300 +F 0 "C?" H 3860 2370 50 0000 L CNN +F 1 "18pF" H 3860 2220 50 0000 L CNN +F 2 "Capacitors_SMD:C_0603_HandSoldering" H 3850 2300 50 0001 C CNN +F 3 "" H 3850 2300 50 0001 C CNN + 1 3850 2300 + 1 0 0 -1 +$EndComp +$Comp +L reform-motherboard-rescue:GND #PWR? +U 1 1 5D1A9B19 +P 3850 2400 +F 0 "#PWR?" H 3850 2150 50 0001 C CNN +F 1 "GND" H 3850 2250 50 0000 C CNN +F 2 "" H 3850 2400 50 0001 C CNN +F 3 "" H 3850 2400 50 0001 C CNN + 1 3850 2400 + 1 0 0 -1 +$EndComp +$Comp +L reform-motherboard-rescue:C_Small C? +U 1 1 5D1A9B1F +P 3250 2300 +F 0 "C?" H 3260 2370 50 0000 L CNN +F 1 "18pF" H 3260 2220 50 0000 L CNN +F 2 "Capacitors_SMD:C_0603_HandSoldering" H 3250 2300 50 0001 C CNN +F 3 "" H 3250 2300 50 0001 C CNN + 1 3250 2300 + 1 0 0 -1 +$EndComp +$Comp +L reform-motherboard-rescue:GND #PWR? +U 1 1 5D1A9B25 +P 3250 2400 +F 0 "#PWR?" H 3250 2150 50 0001 C CNN +F 1 "GND" H 3250 2250 50 0000 C CNN +F 2 "" H 3250 2400 50 0001 C CNN +F 3 "" H 3250 2400 50 0001 C CNN + 1 3250 2400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3650 2200 3850 2200 +Wire Wire Line + 2500 2200 3250 2200 +Connection ~ 3250 2200 +Connection ~ 3850 2200 +Wire Wire Line + 3250 2200 3250 1950 +Wire Wire Line + 3250 1950 3450 1950 +Wire Wire Line + 3650 1950 3850 1950 +Wire Wire Line + 3850 1950 3850 2200 +Wire Wire Line + 3250 2200 3450 2200 +Wire Wire Line + 3850 2200 4600 2200 +Text GLabel 7050 2650 0 50 Output ~ 0 +USB1_TX_N +Text GLabel 7050 2550 0 50 Output ~ 0 +USB1_TX_P +Text GLabel 7050 3050 0 50 Output ~ 0 +USB1_DN +Text GLabel 7050 2950 0 50 Output ~ 0 +USB1_DP +Text GLabel 7050 2850 0 50 Input ~ 0 +USB1_RX_N +Text GLabel 7050 2750 0 50 Input ~ 0 +USB1_RX_P +$Comp +L power:GND #PWR? +U 1 1 5D1C1DA2 +P 8350 5400 +F 0 "#PWR?" H 8350 5150 50 0001 C CNN +F 1 "GND" H 8355 5227 50 0000 C CNN +F 2 "" H 8350 5400 50 0001 C CNN +F 3 "" H 8350 5400 50 0001 C CNN + 1 8350 5400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8350 5400 8350 5350 +$EndSCHEMATC diff --git a/reform2-motherboard/reform2-motherboard/reform2.lib b/reform2-motherboard/reform2-motherboard/reform2.lib @@ -1,6 +1,461 @@ EESchema-LIBRARY Version 2.4 #encoding utf-8 # +# CM2020-00TR +# +DEF CM2020-00TR U? 0 40 Y Y 1 F N +F0 "U?" -903 1244 50 H V L BNN +F1 "CM2020-00TR" -300 900 50 H V L BNN +F2 "TSSOP50P640X120-38N" -450 -2150 50 H I L BNN +F3 "" 0 0 50 H I L BNN +F4 "CM2020-00TR Series 10.8 V HDMI Transmitter Port Protection and Interface Device" -1450 -1950 50 H I L BNN "Field6" +F5 "ON Semiconductor" -350 -2050 50 H I L BNN "Field8" +DRAW +S -900 1200 900 -1200 0 0 10 f +X 5V_SUPPLY 1 1100 1100 200 L 40 40 0 0 W +X TMDS_D0+ 10 -1100 300 200 R 40 40 0 0 I +X TMDS_GND 11 -250 -1400 200 U 40 40 0 0 W +X TMDS_D0- 12 -1100 200 200 R 40 40 0 0 I +X TMDS_CK+ 13 -1100 600 200 R 40 40 0 0 I +X TMDS_GND 14 -150 -1400 200 U 40 40 0 0 W +X TMDS_CK- 15 -1100 500 200 R 40 40 0 0 I +X CE_REMOTE_IN 16 1100 -500 200 L 40 40 0 0 I +X DDC_CLK_IN 17 1100 400 200 L 40 40 0 0 I C +X DDC_DAT_IN 18 1100 100 200 L 40 40 0 0 I +X HOTPLUG_DET_IN 19 1100 -200 200 L 40 40 0 0 I +X LV_SUPPLY 2 1100 1000 200 L 40 40 0 0 W +X HOTPLUG_DET_OUT 20 1100 -300 200 L 40 40 0 0 O +X DDC_DAT_OUT 21 1100 0 200 L 40 40 0 0 O +X DDC_CLK_OUT 22 1100 300 200 L 40 40 0 0 O C +X CE_REMOTE_OUT 23 1100 -600 200 L 40 40 0 0 O +X TMDS_CK- 24 -1100 500 200 R 40 40 0 0 I +X TMDS_GND 25 150 -1400 200 U 40 40 0 0 W +X TMDS_CK+ 26 -1100 600 200 R 40 40 0 0 I +X TMDS_D0- 27 -1100 200 200 R 40 40 0 0 I +X TMDS_GND 28 250 -1400 200 U 40 40 0 0 W +X TMDS_D0+ 29 -1100 300 200 R 40 40 0 0 I +X GND 3 -550 -1400 200 U 40 40 0 0 W +X TMDS_D1- 30 -1100 -100 200 R 40 40 0 0 I +X TMDS_GND 31 350 -1400 200 U 40 40 0 0 W +X TMDS_D1+ 32 -1100 0 200 R 40 40 0 0 I +X TMDS_D2- 33 -1100 -400 200 R 40 40 0 0 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1740 510 1660 N +P 2 0 0 10 500 -1600 600 -1600 N +P 2 0 0 8 510 -740 535 -660 N +P 2 0 0 8 510 60 535 140 N +P 2 0 0 8 510 860 535 940 N +P 2 0 0 8 510 1660 535 1740 N +P 2 0 0 6 525 -2000 575 -1900 N +P 2 0 0 6 525 -1900 475 -2000 N +P 2 0 0 6 525 -1900 475 -1900 N +P 2 0 0 6 525 -1900 725 -1900 N +P 2 0 0 8 535 -660 560 -740 N +P 2 0 0 8 535 140 560 60 N +P 2 0 0 8 535 940 560 860 N +P 2 0 0 8 535 1740 560 1660 N +P 2 0 0 8 560 -740 570 -700 N +P 2 0 0 8 560 60 570 100 N +P 2 0 0 8 560 860 570 900 N +P 2 0 0 8 560 1660 570 1700 N +P 2 0 0 6 575 -2000 625 -1900 N +P 2 0 0 6 600 -1900 600 -1800 N +P 2 0 0 6 600 -1800 600 -1640 N +P 2 0 0 10 600 -1600 600 -1300 N +P 2 0 0 10 600 -1600 700 -1600 N +P 2 0 0 10 600 -1300 700 -1300 N +P 2 0 0 6 625 -2000 675 -1900 N +P 2 0 0 10 700 -1300 700 -700 N +P 2 0 0 6 700 -700 569 -700 N +P 2 0 0 6 700 100 569 100 N +P 2 0 0 6 700 100 700 -700 N +P 2 0 0 6 700 900 569 900 N +P 2 0 0 6 700 900 700 100 N +P 2 0 0 6 700 1700 569 1700 N +P 2 0 0 6 700 1700 700 900 N +P 2 0 0 6 725 -1900 675 -2000 N +P 2 0 0 10 800 -2100 -800 -2100 N +P 2 0 0 6 800 -1800 600 -1800 N +P 2 0 0 10 800 -1800 800 -2100 N +P 2 0 0 10 800 2100 800 -1800 N +P 3 0 0 6 -270 -1620 -285 -1655 -305 -1635 F +P 3 0 0 6 -265 -1935 -300 -1920 -280 -1900 F +P 3 0 0 6 -265 -1665 -280 -1700 -300 -1680 F +P 3 0 0 6 -265 -1335 -300 -1320 -280 -1300 F +P 3 0 0 6 -220 -1930 -255 -1915 -235 -1895 F +P 3 0 0 6 -220 -1330 -255 -1315 -235 -1295 F +X TRCT3 1 -1000 900 200 R 40 40 0 0 P +X TDR1- 10 -1000 -1000 200 R 40 40 0 0 P +X TDR1+ 11 -1000 -400 200 R 40 40 0 0 P +X TRCT1 12 -1000 -700 200 R 40 40 0 0 P +X YEL- 13 -1000 -1400 200 R 40 40 0 0 P +X YEL+ 14 -1000 -1200 200 R 40 40 0 0 P +X ORN- 15 -1000 -1600 200 R 40 40 0 0 P +X COM+ 16 -1000 -1800 200 R 40 40 0 0 P +X GRN- 17 -1000 -2000 200 R 40 40 0 0 P +X TRD3- 2 -1000 600 200 R 40 40 0 0 P +X TRD3+ 3 -1000 1200 200 R 40 40 0 0 P +X TRD2+ 4 -1000 400 200 R 40 40 0 0 P +X TRD2- 5 -1000 -200 200 R 40 40 0 0 P +X TRCT2 6 -1000 100 200 R 40 40 0 0 P +X TRCT4 7 -1000 1700 200 R 40 40 0 0 P +X TRD4+ 8 -1000 2000 200 R 40 40 0 0 P +X TRD4- 9 -1000 1400 200 R 40 40 0 0 P +X SHIELD SH1 1000 -1800 200 L 40 40 0 0 I +X SHIELD SH2 1000 -1800 200 L 40 40 0 0 I +ENDDRAW +ENDDEF +# # LTC4162-F # DEF LTC4162-F U 0 40 Y Y 1 F N @@ -42,6 +497,83 @@ X NTCBIAS 9 550 -450 100 L 50 50 1 1 U ENDDRAW ENDDEF # +# SN65DSI86ZQER +# +DEF SN65DSI86ZQER U 0 40 Y Y 1 F N +F0 "U" -628 1752 50 H V L BNN +F1 "SN65DSI86ZQER" -596 -2192 50 H V L BNN +F2 "BGA64C50P9X9_500X500X100" -550 -2650 50 H I L BNN +F3 "" 0 0 50 H I L BNN +F4 "Dual-Channel MIPI® DSI to Embedded DisplayPort™ _eDP _ Bridge 64-BGA MICROSTAR JUNIOR -40 to 85" -2100 -2500 50 H I L BNN +DRAW +S -600 1700 850 -2100 1 1 10 f +X ADDR 1 -700 -1350 100 R 40 40 0 0 B +X DB2P 10 -700 100 100 R 40 40 0 0 I +X DB2N 11 -700 0 100 R 40 40 0 0 I +X DB3P 12 -700 -100 100 R 40 40 0 0 I +X DB3N 13 -700 -200 100 R 40 40 0 0 I +X SCL 15 -700 -1500 100 R 40 40 0 0 B C +X SDA 16 -700 -1600 100 R 40 40 0 0 B +X VCC 17 950 -900 100 L 40 40 0 0 W +X VCCA 18 350 1800 100 D 50 50 0 0 W +X DA0P 19 -700 1600 100 R 40 40 0 0 I +X ~EN~ 2 950 -400 100 L 40 40 0 0 I +X DA0N 20 -700 1500 100 R 40 40 0 0 B +X DA1P 21 -700 1400 100 R 40 40 0 0 I +X DA1N 22 -700 1300 100 R 40 40 0 0 I +X GND 23 450 -2200 100 U 40 40 0 0 W +X DACP 24 -700 800 100 R 40 40 0 0 I +X DACN 25 -700 700 100 R 40 40 0 0 I +X GND 26 350 -2200 100 U 40 40 0 0 W +X DA2P 27 -700 1200 100 R 40 40 0 0 I +X DA2N 28 -700 1100 100 R 40 40 0 0 I +X DA3P 29 -700 1000 100 R 40 40 0 0 I +X VCCA 3 450 1800 100 D 50 50 0 0 W +X DA3N 30 -700 900 100 R 40 40 0 0 I +X VCCA 31 250 1800 100 D 50 50 0 0 W +X HPD 32 950 -300 100 L 40 40 0 0 I +X VCC 33 950 -800 100 L 40 40 0 0 W +X AUXP 34 950 300 100 L 40 40 0 0 B +X AUXN 35 950 400 100 L 40 40 0 0 B +X VCCA 36 150 1800 100 D 50 50 0 0 W +X ML0P 37 950 600 100 L 40 40 0 0 O +X ML0N 38 950 700 100 L 40 40 0 0 O +X ML1P 39 950 900 100 L 40 40 0 0 O +X DB0P 4 -700 500 100 R 40 40 0 0 I +X ML1N 40 950 1000 100 L 40 40 0 0 O +X VCCA 41 -250 1800 100 D 50 50 0 0 W +X VPLL 42 950 -1800 100 L 40 40 0 0 W +X VCCA 43 -150 1800 100 D 50 50 0 0 W +X ML2P 44 950 1200 100 L 40 40 0 0 O +X ML2N 45 950 1300 100 L 40 40 0 0 O +X ML3P 46 950 1500 100 L 40 40 0 0 O +X ML3N 47 950 1600 100 L 40 40 0 0 O +X VCCA 48 -50 1800 100 D 50 50 0 0 W +X VCCA 49 50 1800 100 D 50 50 0 0 W +X DB0N 5 -700 400 100 R 40 40 0 0 I +X TEST3 50 -700 -2000 100 R 40 40 0 0 B +X REFCLK 51 950 -200 100 L 40 40 0 0 I C +X GND 52 150 -2200 100 U 40 40 0 0 W +X VCCIO 53 950 -1600 100 L 40 40 0 0 W +X GPIO3 54 -700 -750 100 R 40 40 0 0 B +X TEST2 55 -700 -1900 100 R 40 40 0 0 B +X GPIO2 56 -700 -850 100 R 40 40 0 0 B +X GPIO4 57 -700 -650 100 R 40 40 0 0 B +X GPIO1 58 -700 -950 100 R 40 40 0 0 B +X VCC 59 950 -700 100 L 40 40 0 0 W +X DB1P 6 -700 300 100 R 40 40 0 0 I +X TEST1 60 -700 -1800 100 R 40 40 0 0 I +X IRQ 61 -700 -1200 100 R 40 40 0 0 O +X VCC 62 950 -600 100 L 40 40 0 0 W +X VCCIO 63 950 -1700 100 L 40 40 0 0 W +X GND 64 250 -2200 100 U 40 40 0 0 W +X GND 65 550 -2200 100 U 40 40 0 0 W +X DB1N 7 -700 200 100 R 40 40 0 0 I +X DBCP 8 -700 -300 100 R 40 40 0 0 I +X DBCN 9 -700 -400 100 R 40 40 0 0 I +ENDDRAW +ENDDEF +# # phycore-imx8m-alpha # DEF phycore-imx8m-alpha U 0 40 Y Y 1 F N