reform

MNT Reform: Open Source Portable Computer
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commit ea3dce1ebc1dede56f8b4fe312beacae653528f6
parent a3df16500ff1b60cce700743549c1e925bf0b85d
Author: mntmn <lukas@mntmn.com>
Date:   Wed, 29 Jan 2020 22:18:35 +0100

WIP snapshot of reform2 batterypack PCB

Diffstat:
Areform2-batterypack/reform2-batterypack-cache.lib | 79+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Areform2-batterypack/reform2-batterypack.kicad_pcb | 867+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Areform2-batterypack/reform2-batterypack.pro | 249+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Areform2-batterypack/reform2-batterypack.sch | 189+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Areform2-batterypack/reform2-batterypack.stl | 0
Areform2-batterypack/sym-lib-table | 3+++
6 files changed, 1387 insertions(+), 0 deletions(-)

diff --git a/reform2-batterypack/reform2-batterypack-cache.lib b/reform2-batterypack/reform2-batterypack-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# Connector_Conn_01x05_Female +# +DEF Connector_Conn_01x05_Female J 0 40 Y N 1 F N +F0 "J" 0 300 50 H V C CNN +F1 "Connector_Conn_01x05_Female" 0 -300 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + Connector*:*_1x??_* +$ENDFPLIST +DRAW +A 0 -200 20 901 -901 1 1 6 N 0 -180 0 -220 +A 0 -100 20 901 -901 1 1 6 N 0 -80 0 -120 +A 0 0 20 901 -901 1 1 6 N 0 20 0 -20 +A 0 100 20 901 -901 1 1 6 N 0 120 0 80 +A 0 200 20 901 -901 1 1 6 N 0 220 0 180 +P 2 1 1 6 -50 -200 -20 -200 N +P 2 1 1 6 -50 -100 -20 -100 N +P 2 1 1 6 -50 0 -20 0 N +P 2 1 1 6 -50 100 -20 100 N +P 2 1 1 6 -50 200 -20 200 N +X Pin_1 1 -200 200 150 R 50 50 1 1 P +X Pin_2 2 -200 100 150 R 50 50 1 1 P +X Pin_3 3 -200 0 150 R 50 50 1 1 P +X Pin_4 4 -200 -100 150 R 50 50 1 1 P +X Pin_5 5 -200 -200 150 R 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Mechanical_MountingHole +# +DEF Mechanical_MountingHole H 0 40 Y Y 1 F N +F0 "H" 0 200 50 H V C CNN +F1 "Mechanical_MountingHole" 0 125 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + MountingHole* +$ENDFPLIST +DRAW +C 0 0 50 0 1 50 N +ENDDRAW +ENDDEF +# +# reform2-batterypack_KEYSTONE_54 +# +DEF reform2-batterypack_KEYSTONE_54 U 0 40 Y Y 1 F N +F0 "U" -50 650 50 H V L BNN +F1 "reform2-batterypack_KEYSTONE_54" -250 750 50 H V L BNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + KEYESTONE_54_18650 + KEYESTONE_54_18650_3D + KEYESTONE_54_A_TYPE_3D + KEYESTONE_54_A_TYPE +$ENDFPLIST +DRAW +P 2 0 0 12 -150 100 0 100 N +P 2 0 0 12 -100 50 0 50 N +P 2 0 0 12 0 50 0 -150 N +P 2 0 0 12 0 50 100 50 N +P 2 0 0 12 0 100 150 100 N +P 2 0 0 12 0 300 0 100 N +P 2 0 0 12 80 200 120 200 N +P 2 0 0 12 100 220 100 180 N +X + 1 0 300 0 D 40 40 0 0 B +X + 2 0 300 0 D 40 40 0 0 B +X + 3 0 300 0 D 40 40 0 0 B +X - 4 0 -150 0 U 40 40 0 0 B +X - 5 0 -150 0 U 40 40 0 0 B +X - 6 0 -150 0 U 40 40 0 0 B +ENDDRAW +ENDDEF +# +#End Library diff --git a/reform2-batterypack/reform2-batterypack.kicad_pcb b/reform2-batterypack/reform2-batterypack.kicad_pcb @@ -0,0 +1,867 @@ +(kicad_pcb (version 20171130) (host pcbnew 5.1.2+dfsg1-1) + + (general + (thickness 1.6) + (drawings 17) + (tracks 57) + (zones 0) + (modules 10) + (nets 6) + ) + + (page A4) + (layers + (0 F.Cu signal) + (31 B.Cu signal) + (32 B.Adhes user) + (33 F.Adhes user) + (34 B.Paste user) + (35 F.Paste user) + (36 B.SilkS user) + (37 F.SilkS user) + (38 B.Mask user) + (39 F.Mask user) + (40 Dwgs.User user) + (41 Cmts.User user) + (42 Eco1.User user) + (43 Eco2.User user) + (44 Edge.Cuts user) + (45 Margin user) + (46 B.CrtYd user) + (47 F.CrtYd user) + (48 B.Fab user) + (49 F.Fab user hide) + ) + + (setup + (last_trace_width 0.25) + (trace_clearance 0.2) + (zone_clearance 0.508) + (zone_45_only no) + (trace_min 0.2) + (via_size 0.8) + (via_drill 0.4) + (via_min_size 0.4) + (via_min_drill 0.3) + (uvia_size 0.3) + (uvia_drill 0.1) + (uvias_allowed no) + (uvia_min_size 0.2) + (uvia_min_drill 0.1) + (edge_width 0.05) + (segment_width 0.2) + (pcb_text_width 0.3) + (pcb_text_size 1.5 1.5) + (mod_edge_width 0.12) + (mod_text_size 1 1) + (mod_text_width 0.15) + (pad_size 1.524 1.524) + (pad_drill 0.762) + (pad_to_mask_clearance 0.051) + (solder_mask_min_width 0.25) + (aux_axis_origin 0 0) + (visible_elements FFFFFF7F) + (pcbplotparams + (layerselection 0x010fc_ffffffff) + (usegerberextensions false) + (usegerberattributes false) + (usegerberadvancedattributes false) + (creategerberjobfile false) + (excludeedgelayer true) + (linewidth 0.100000) + (plotframeref false) + (viasonmask false) + (mode 1) + (useauxorigin false) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15.000000) + (psnegative false) + (psa4output false) + (plotreference true) + (plotvalue true) + (plotinvisibletext false) + (padsonsilk false) + (subtractmaskfromsilk false) + (outputformat 1) + (mirror false) + (drillshape 0) + (scaleselection 1) + (outputdirectory "gerbers-d2")) + ) + + (net 0 "") + (net 1 "Net-(J1-Pad5)") + (net 2 "Net-(J1-Pad4)") + (net 3 "Net-(J1-Pad3)") + (net 4 "Net-(J1-Pad2)") + (net 5 "Net-(J1-Pad1)") + + (net_class Default "This is the default net class." + (clearance 0.2) + (trace_width 0.25) + (via_dia 0.8) + (via_drill 0.4) + (uvia_dia 0.3) + (uvia_drill 0.1) + ) + + (net_class PWR "" + (clearance 0.2) + (trace_width 1.5) + (via_dia 0.8) + (via_drill 0.4) + (uvia_dia 0.3) + (uvia_drill 0.1) + (add_net "Net-(J1-Pad1)") + (add_net "Net-(J1-Pad2)") + (add_net "Net-(J1-Pad3)") + (add_net "Net-(J1-Pad4)") + (add_net "Net-(J1-Pad5)") + ) + + (module Symbol:WEEE-Logo_4.2x6mm_SilkScreen (layer F.Cu) (tedit 0) (tstamp 5DC6C547) + (at 113 93) + (descr "Waste Electrical and Electronic Equipment Directive") + (tags "Logo WEEE") + (attr virtual) + (fp_text reference REF** (at 0 0) (layer F.SilkS) hide + (effects (font (size 1 1) (thickness 0.15))) + ) + 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M2") + (tags "mounting hole 2.2mm no annular m2") + (path /5DC7B8FF) + (attr virtual) + (fp_text reference H4 (at 0 -3.2) (layer F.SilkS) hide + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value MountingHole (at 0 3.2) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_circle (center 0 0) (end 2.45 0) (layer F.CrtYd) (width 0.05)) + (fp_circle (center 0 0) (end 2.2 0) (layer Cmts.User) (width 0.15)) + (fp_text user %R (at 0.3 0) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (pad 1 np_thru_hole circle (at 0 0) (size 2.2 2.2) (drill 2.2) (layers *.Cu *.Mask)) + ) + + (module MountingHole:MountingHole_2.2mm_M2 (layer F.Cu) (tedit 56D1B4CB) (tstamp 5D9AFD19) + (at 113 138) + (descr "Mounting Hole 2.2mm, no annular, M2") + (tags "mounting hole 2.2mm no annular m2") + (path /5DC7B6D8) + (attr virtual) + (fp_text reference H3 (at 0 -3.2) (layer F.SilkS) hide + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value MountingHole (at 0 3.2) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_circle (center 0 0) (end 2.45 0) (layer F.CrtYd) (width 0.05)) + (fp_circle (center 0 0) (end 2.2 0) (layer Cmts.User) (width 0.15)) + (fp_text user %R (at 0.3 0) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (pad 1 np_thru_hole circle (at 0 0) (size 2.2 2.2) (drill 2.2) (layers *.Cu *.Mask)) + ) + + (module MountingHole:MountingHole_2.2mm_M2 (layer F.Cu) (tedit 56D1B4CB) (tstamp 5D9AFF23) + (at 159 104) + (descr "Mounting Hole 2.2mm, no annular, M2") + (tags "mounting hole 2.2mm no annular m2") + (path /5DC7B332) + (attr virtual) + (fp_text reference H2 (at 0 -3.2) (layer F.SilkS) hide + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value MountingHole (at 0 3.2) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_circle (center 0 0) (end 2.45 0) (layer F.CrtYd) (width 0.05)) + (fp_circle (center 0 0) (end 2.2 0) (layer Cmts.User) (width 0.15)) + (fp_text user %R (at 0.3 0) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (pad 1 np_thru_hole circle (at 0 0) (size 2.2 2.2) (drill 2.2) (layers *.Cu *.Mask)) + ) + + (module MountingHole:MountingHole_2.2mm_M2 (layer F.Cu) (tedit 56D1B4CB) (tstamp 5D9B3339) + (at 113 104) + (descr "Mounting Hole 2.2mm, no annular, M2") + (tags "mounting hole 2.2mm no annular m2") + (path /5DC7B165) + (attr virtual) + (fp_text reference H1 (at 0 -3.2) (layer F.SilkS) hide + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value MountingHole (at 0 3.2) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_circle (center 0 0) (end 2.45 0) (layer F.CrtYd) (width 0.05)) + (fp_circle (center 0 0) (end 2.2 0) (layer Cmts.User) (width 0.15)) + (fp_text user %R (at 0.3 0) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (pad 1 np_thru_hole circle (at 0 0) (size 2.2 2.2) (drill 2.2) (layers *.Cu *.Mask)) + ) + + (gr_text "MNT Reform Battery Board D-2\n2019-11-09 MNT Research GmbH" (at 113 134.25 90) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15)) (justify left)) + ) + (dimension 17.5 (width 0.15) (layer Dwgs.User) + (gr_text "17.500 mm" (at 167.75 161.05) (layer Dwgs.User) + (effects (font (size 1 1) (thickness 0.15))) + ) + (feature1 (pts (xy 176.5 138) (xy 176.5 160.336421))) + (feature2 (pts (xy 159 138) (xy 159 160.336421))) + (crossbar (pts (xy 159 159.75) (xy 176.5 159.75))) + (arrow1a (pts (xy 176.5 159.75) (xy 175.373496 160.336421))) + (arrow1b (pts (xy 176.5 159.75) (xy 175.373496 159.163579))) + (arrow2a (pts (xy 159 159.75) (xy 160.126504 160.336421))) + (arrow2b (pts (xy 159 159.75) (xy 160.126504 159.163579))) + ) + (dimension 17.5 (width 0.15) (layer Dwgs.User) + (gr_text "17.500 mm" (at 104.25 161.3) (layer Dwgs.User) + (effects (font (size 1 1) (thickness 0.15))) + ) + (feature1 (pts (xy 113 136.5) (xy 113 160.586421))) + (feature2 (pts (xy 95.5 136.5) (xy 95.5 160.586421))) + (crossbar (pts (xy 95.5 160) (xy 113 160))) + (arrow1a (pts (xy 113 160) (xy 111.873496 160.586421))) + (arrow1b (pts (xy 113 160) (xy 111.873496 159.413579))) + (arrow2a (pts (xy 95.5 160) (xy 96.626504 160.586421))) + (arrow2b (pts (xy 95.5 160) (xy 96.626504 159.413579))) + ) + (dimension 81 (width 0.15) (layer Dwgs.User) + (gr_text "81.000 mm" (at 136 80.2) (layer Dwgs.User) + (effects (font (size 1 1) (thickness 0.15))) + ) + (feature1 (pts (xy 176.5 87.5) (xy 176.5 80.913579))) + (feature2 (pts (xy 95.5 87.5) (xy 95.5 80.913579))) + (crossbar (pts (xy 95.5 81.5) (xy 176.5 81.5))) + (arrow1a (pts (xy 176.5 81.5) (xy 175.373496 82.086421))) + (arrow1b (pts (xy 176.5 81.5) (xy 175.373496 80.913579))) + (arrow2a (pts (xy 95.5 81.5) (xy 96.626504 82.086421))) + (arrow2b (pts (xy 95.5 81.5) (xy 96.626504 80.913579))) + ) + (dimension 92.5 (width 0.15) (layer Dwgs.User) + (gr_text "92.500 mm" (at 141.75 76.95) (layer Dwgs.User) + (effects (font (size 1 1) (thickness 0.15))) + ) + (feature1 (pts (xy 188 87.75) (xy 188 77.663579))) + (feature2 (pts (xy 95.5 87.75) (xy 95.5 77.663579))) + (crossbar (pts (xy 95.5 78.25) (xy 188 78.25))) + (arrow1a (pts (xy 188 78.25) (xy 186.873496 78.836421))) + (arrow1b (pts (xy 188 78.25) (xy 186.873496 77.663579))) + (arrow2a (pts (xy 95.5 78.25) (xy 96.626504 78.836421))) + (arrow2b (pts (xy 95.5 78.25) (xy 96.626504 77.663579))) + ) + (gr_line (start 179.5 135.25) (end 176.5 138.5) (layer Edge.Cuts) (width 0.05) (tstamp 5DC33F17)) + (gr_line (start 183.5 135.25) (end 179.5 135.25) (layer Edge.Cuts) (width 0.05) (tstamp 5DC33F1A)) + (gr_line (start 186.5 132.25) (end 183.5 135.25) (layer Edge.Cuts) (width 0.05) (tstamp 5DC55B4F)) + (gr_line (start 186.5 108.25) (end 186.5 132.25) (layer Edge.Cuts) (width 0.05) (tstamp 5DC55B55)) + (gr_line (start 183.5 105.25) (end 186.5 108.25) (layer Edge.Cuts) (width 0.05) (tstamp 5DC55B52)) + (gr_line (start 179.5 105.25) (end 183.5 105.25) (layer Edge.Cuts) (width 0.05)) + (gr_line (start 176.5 102) (end 179.5 105.25) (layer Edge.Cuts) (width 0.05)) + (gr_line (start 176.5 153) (end 176.5 138.5) (layer Edge.Cuts) (width 0.05) (tstamp 5DC33CEB)) + (gr_line (start 176.5 102) (end 176.5 87.5) (layer Edge.Cuts) (width 0.05) (tstamp 5D9B12DD)) + (gr_line (start 95.5 153) (end 95.5 87.5) (layer Edge.Cuts) (width 0.05) (tstamp 5D9661A0)) + (gr_line (start 176.5 153) (end 95.5 153) (layer Edge.Cuts) (width 0.05)) + (gr_line (start 95.5 87.5) (end 176.5 87.5) (layer Edge.Cuts) (width 0.05)) + + (segment (start 104 92.95) (end 101.46 90.41) (width 1.5) (layer F.Cu) (net 1)) + (segment (start 104 98.03) (end 104 92.95) (width 1.5) (layer F.Cu) (net 1)) + (segment (start 104 98.03) (end 98.92 98.03) (width 1.5) (layer F.Cu) (net 1)) + (segment (start 182 115.25) (end 115.25 115.25) (width 1.5) (layer F.Cu) (net 1)) + (segment (start 104 104) (end 104 98.03) (width 1.5) (layer F.Cu) (net 1)) + (segment (start 115.25 115.25) (end 104 104) (width 1.5) (layer F.Cu) (net 1)) + (segment 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120.25) (width 1.5) (layer F.Cu) (net 3)) + (segment (start 172.358031 103.858031) (end 178.5 110) (width 1.5) (layer F.Cu) (net 3)) + (segment (start 183.600001 119.899999) (end 182.571999 119.899999) (width 1.5) (layer F.Cu) (net 3)) + (segment (start 181.1 110) (end 185.1 114) (width 1.5) (layer F.Cu) (net 3)) + (segment (start 150 98.03) (end 151.47 99.5) (width 1.5) (layer F.Cu) (net 3)) + (segment (start 151.47 99.5) (end 161.5 99.5) (width 1.5) (layer F.Cu) (net 3)) + (segment (start 178.5 110) (end 181.1 110) (width 1.5) (layer F.Cu) (net 3)) + (segment (start 185.1 114) (end 185.1 118.4) (width 1.5) (layer F.Cu) (net 3)) + (segment (start 185.1 118.4) (end 183.600001 119.899999) (width 1.5) (layer F.Cu) (net 3)) + (segment (start 168 147.8) (end 170.54 150.34) (width 1.5) (layer F.Cu) (net 4)) + (segment (start 168 142.72) (end 168 147.8) (width 1.5) (layer F.Cu) (net 4)) + (segment (start 144.92 147.83) (end 147.46 150.37) (width 1.5) (layer F.Cu) (net 4)) + (segment (start 144.92 142.75) (end 144.92 147.83) (width 1.5) (layer F.Cu) (net 4)) + (segment (start 144.92 142.75) (end 150 142.75) (width 1.5) (layer F.Cu) (net 4)) + (segment (start 168 142.72) (end 173.08 142.72) (width 1.5) (layer F.Cu) (net 4)) + (segment (start 173.08 140.233813) (end 173.08 142.72) (width 1.5) (layer F.Cu) (net 4)) + (segment (start 173.08 129.07) (end 173.08 140.233813) (width 1.5) (layer F.Cu) (net 4)) + (segment (start 179.4 122.75) (end 173.08 129.07) (width 1.5) (layer F.Cu) (net 4)) + (segment (start 182 122.75) (end 179.4 122.75) (width 1.5) (layer F.Cu) (net 4)) + (segment (start 167.97 142.75) (end 168 142.72) (width 1.5) (layer F.Cu) (net 4)) + (segment (start 150 142.75) (end 167.97 142.75) (width 1.5) (layer F.Cu) (net 4)) + (segment (start 173.08 100.486187) (end 173.08 98) (width 1.5) (layer B.Cu) (net 5)) + (segment (start 180.8 125.25) (end 173.08 117.53) (width 1.5) (layer B.Cu) (net 5)) + (segment (start 173.08 117.53) (end 173.08 100.486187) (width 1.5) (layer B.Cu) (net 5)) + (segment (start 182 125.25) (end 180.8 125.25) (width 1.5) (layer B.Cu) (net 5)) + (segment (start 173.08 98) (end 168 98) (width 1.5) (layer B.Cu) (net 5)) + (segment (start 173.08 92.92) (end 170.54 90.38) (width 1.5) (layer B.Cu) (net 5)) + (segment (start 173.08 98) (end 173.08 92.92) (width 1.5) (layer B.Cu) (net 5)) + +) diff --git a/reform2-batterypack/reform2-batterypack.pro b/reform2-batterypack/reform2-batterypack.pro @@ -0,0 +1,249 @@ +update=Sun Oct 6 22:01:56 2019 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +[pcbnew] +version=1 +PageLayoutDescrFile= +LastNetListRead= +CopperLayerCount=2 +BoardThickness=1.6 +AllowMicroVias=0 +AllowBlindVias=0 +RequireCourtyardDefinitions=0 +ProhibitOverlappingCourtyards=1 +MinTrackWidth=0.2 +MinViaDiameter=0.4 +MinViaDrill=0.3 +MinMicroViaDiameter=0.2 +MinMicroViaDrill=0.09999999999999999 +MinHoleToHole=0.25 +TrackWidth1=0.25 +ViaDiameter1=0.8 +ViaDrill1=0.4 +dPairWidth1=0.2 +dPairGap1=0.25 +dPairViaGap1=0.25 +SilkLineWidth=0.12 +SilkTextSizeV=1 +SilkTextSizeH=1 +SilkTextSizeThickness=0.15 +SilkTextItalic=0 +SilkTextUpright=1 +CopperLineWidth=0.2 +CopperTextSizeV=1.5 +CopperTextSizeH=1.5 +CopperTextThickness=0.3 +CopperTextItalic=0 +CopperTextUpright=1 +EdgeCutLineWidth=0.05 +CourtyardLineWidth=0.05 +OthersLineWidth=0.15 +OthersTextSizeV=1 +OthersTextSizeH=1 +OthersTextSizeThickness=0.15 +OthersTextItalic=0 +OthersTextUpright=1 +SolderMaskClearance=0.051 +SolderMaskMinWidth=0.25 +SolderPasteClearance=0 +SolderPasteRatio=-0 +[pcbnew/Layer.F.Cu] +Name=F.Cu +Type=0 +Enabled=1 +[pcbnew/Layer.In1.Cu] +Name=In1.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In2.Cu] +Name=In2.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In3.Cu] +Name=In3.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In4.Cu] +Name=In4.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In5.Cu] +Name=In5.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In6.Cu] +Name=In6.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In7.Cu] +Name=In7.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In8.Cu] +Name=In8.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In9.Cu] +Name=In9.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In10.Cu] +Name=In10.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In11.Cu] +Name=In11.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In12.Cu] +Name=In12.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In13.Cu] +Name=In13.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In14.Cu] +Name=In14.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In15.Cu] +Name=In15.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In16.Cu] +Name=In16.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In17.Cu] +Name=In17.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In18.Cu] +Name=In18.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In19.Cu] +Name=In19.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In20.Cu] +Name=In20.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In21.Cu] +Name=In21.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In22.Cu] +Name=In22.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In23.Cu] +Name=In23.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In24.Cu] +Name=In24.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In25.Cu] +Name=In25.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In26.Cu] +Name=In26.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In27.Cu] +Name=In27.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In28.Cu] +Name=In28.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In29.Cu] +Name=In29.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In30.Cu] +Name=In30.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.B.Cu] +Name=B.Cu +Type=0 +Enabled=1 +[pcbnew/Layer.B.Adhes] +Enabled=1 +[pcbnew/Layer.F.Adhes] +Enabled=1 +[pcbnew/Layer.B.Paste] +Enabled=1 +[pcbnew/Layer.F.Paste] +Enabled=1 +[pcbnew/Layer.B.SilkS] +Enabled=1 +[pcbnew/Layer.F.SilkS] +Enabled=1 +[pcbnew/Layer.B.Mask] +Enabled=1 +[pcbnew/Layer.F.Mask] +Enabled=1 +[pcbnew/Layer.Dwgs.User] +Enabled=1 +[pcbnew/Layer.Cmts.User] +Enabled=1 +[pcbnew/Layer.Eco1.User] +Enabled=1 +[pcbnew/Layer.Eco2.User] +Enabled=1 +[pcbnew/Layer.Edge.Cuts] +Enabled=1 +[pcbnew/Layer.Margin] +Enabled=1 +[pcbnew/Layer.B.CrtYd] +Enabled=1 +[pcbnew/Layer.F.CrtYd] +Enabled=1 +[pcbnew/Layer.B.Fab] +Enabled=1 +[pcbnew/Layer.F.Fab] +Enabled=1 +[pcbnew/Layer.Rescue] +Enabled=0 +[pcbnew/Netclasses] +[pcbnew/Netclasses/Default] +Name=Default +Clearance=0.2 +TrackWidth=0.25 +ViaDiameter=0.8 +ViaDrill=0.4 +uViaDiameter=0.3 +uViaDrill=0.1 +dPairWidth=0.2 +dPairGap=0.25 +dPairViaGap=0.25 +[pcbnew/Netclasses/1] +Name=PWR +Clearance=0.2 +TrackWidth=1.5 +ViaDiameter=0.8 +ViaDrill=0.4 +uViaDiameter=0.3 +uViaDrill=0.1 +dPairWidth=0.2 +dPairGap=0.25 +dPairViaGap=0.25 diff --git a/reform2-batterypack/reform2-batterypack.sch b/reform2-batterypack/reform2-batterypack.sch @@ -0,0 +1,189 @@ +EESchema Schematic File Version 4 +LIBS:reform2-batterypack-cache +EELAYER 29 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L reform2-batterypack:KEYSTONE_54 U2 +U 1 1 5F0F9013 +P 3450 2850 +F 0 "U2" H 3450 2850 50 0001 L BNN +F 1 "KEYSTONE_54" H 3200 3600 50 0001 L BNN +F 2 "reform2-batterypack:Keystone54" H 3450 2850 50 0001 C CNN +F 3 "" H 3450 2850 50 0001 C CNN + 1 3450 2850 + 1 0 0 -1 +$EndComp +$Comp +L reform2-batterypack:KEYSTONE_54 U3 +U 1 1 5F0FA857 +P 3900 2850 +F 0 "U3" H 3900 2850 50 0001 L BNN +F 1 "KEYSTONE_54" H 3650 3600 50 0001 L BNN +F 2 "reform2-batterypack:Keystone54" H 3900 2850 50 0001 C CNN +F 3 "" H 3900 2850 50 0001 C CNN + 1 3900 2850 + 1 0 0 -1 +$EndComp +$Comp +L reform2-batterypack:KEYSTONE_54 U4 +U 1 1 5F0FA861 +P 4350 2850 +F 0 "U4" H 4350 2850 50 0001 L BNN +F 1 "KEYSTONE_54" H 4100 3600 50 0001 L BNN +F 2 "reform2-batterypack:Keystone54" H 4350 2850 50 0001 C CNN +F 3 "" H 4350 2850 50 0001 C CNN + 1 4350 2850 + 1 0 0 -1 +$EndComp +$Comp +L reform2-batterypack:KEYSTONE_54 U1 +U 1 1 5F0F7120 +P 3000 2850 +F 0 "U1" H 3000 2850 50 0001 L BNN +F 1 "KEYSTONE_54" H 2750 3600 50 0001 L BNN +F 2 "reform2-batterypack:Keystone54" H 3000 2850 50 0001 C CNN +F 3 "" H 3000 2850 50 0001 C CNN + 1 3000 2850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3000 2550 3000 2400 +Wire Wire Line + 3000 2400 3100 2400 +Wire Wire Line + 3250 2400 3250 3150 +Wire Wire Line + 3250 3150 3450 3150 +Wire Wire Line + 3450 3150 3450 3000 +Wire Wire Line + 3450 2550 3450 2400 +Wire Wire Line + 3450 2400 3550 2400 +Wire Wire Line + 3700 2400 3700 3150 +Wire Wire Line + 3700 3150 3900 3150 +Wire Wire Line + 3900 3150 3900 3000 +Wire Wire Line + 3900 2550 3900 2400 +Wire Wire Line + 3900 2400 4000 2400 +Wire Wire Line + 4150 2400 4150 3150 +Wire Wire Line + 4150 3150 4350 3150 +Wire Wire Line + 4350 3150 4350 3000 +$Comp +L Connector:Conn_01x05_Female J1 +U 1 1 5DC7747A +P 3700 1550 +F 0 "J1" V 3638 1162 50 0000 R CNN +F 1 "Conn_01x05_Female" V 3547 1162 50 0000 R CNN +F 2 "Connector_Molex:Molex_Nano-Fit_105309-xx05_1x05_P2.50mm_Vertical" H 3700 1550 50 0001 C CNN +F 3 "~" H 3700 1550 50 0001 C CNN + 1 3700 1550 + 0 1 -1 0 +$EndComp +Wire Wire Line + 4350 2550 4350 2000 +Wire Wire Line + 4350 2000 3900 2000 +Wire Wire Line + 3800 2100 4000 2100 +Wire Wire Line + 4000 2100 4000 2400 +Connection ~ 4000 2400 +Wire Wire Line + 4000 2400 4150 2400 +Wire Wire Line + 3700 2100 3550 2100 +Wire Wire Line + 3550 2100 3550 2400 +Connection ~ 3550 2400 +Wire Wire Line + 3550 2400 3700 2400 +Wire Wire Line + 3600 2000 3100 2000 +Wire Wire Line + 3100 2000 3100 2400 +Connection ~ 3100 2400 +Wire Wire Line + 3100 2400 3250 2400 +Wire Wire Line + 2800 3150 3000 3150 +Wire Wire Line + 3000 3150 3000 3000 +$Comp +L Mechanical:MountingHole H1 +U 1 1 5DC7B165 +P 1750 2100 +F 0 "H1" H 1850 2146 50 0000 L CNN +F 1 "MountingHole" H 1850 2055 50 0000 L CNN +F 2 "MountingHole:MountingHole_2.2mm_M2" H 1750 2100 50 0001 C CNN +F 3 "~" H 1750 2100 50 0001 C CNN + 1 1750 2100 + 1 0 0 -1 +$EndComp +$Comp +L Mechanical:MountingHole H2 +U 1 1 5DC7B332 +P 1750 2300 +F 0 "H2" H 1850 2346 50 0000 L CNN +F 1 "MountingHole" H 1850 2255 50 0000 L CNN +F 2 "MountingHole:MountingHole_2.2mm_M2" H 1750 2300 50 0001 C CNN +F 3 "~" H 1750 2300 50 0001 C CNN + 1 1750 2300 + 1 0 0 -1 +$EndComp +$Comp +L Mechanical:MountingHole H3 +U 1 1 5DC7B6D8 +P 1750 2500 +F 0 "H3" H 1850 2546 50 0000 L CNN +F 1 "MountingHole" H 1850 2455 50 0000 L CNN +F 2 "MountingHole:MountingHole_2.2mm_M2" H 1750 2500 50 0001 C CNN +F 3 "~" H 1750 2500 50 0001 C CNN + 1 1750 2500 + 1 0 0 -1 +$EndComp +$Comp +L Mechanical:MountingHole H4 +U 1 1 5DC7B8FF +P 1750 2700 +F 0 "H4" H 1850 2746 50 0000 L CNN +F 1 "MountingHole" H 1850 2655 50 0000 L CNN +F 2 "MountingHole:MountingHole_2.2mm_M2" H 1750 2700 50 0001 C CNN +F 3 "~" H 1750 2700 50 0001 C CNN + 1 1750 2700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3500 1750 3500 1850 +Wire Wire Line + 3500 1850 2800 1850 +Wire Wire Line + 2800 1850 2800 3150 +Wire Wire Line + 3600 1750 3600 2000 +Wire Wire Line + 3700 1750 3700 2100 +Wire Wire Line + 3800 1750 3800 2100 +Wire Wire Line + 3900 1750 3900 2000 +$EndSCHEMATC diff --git a/reform2-batterypack/reform2-batterypack.stl b/reform2-batterypack/reform2-batterypack.stl Binary files differ. diff --git a/reform2-batterypack/sym-lib-table b/reform2-batterypack/sym-lib-table @@ -0,0 +1,3 @@ +(sym_lib_table + (lib (name reform2-batterypack)(type Legacy)(uri ${KIPRJMOD}/reform2-batterypack.lib)(options "")(descr "")) +)